Category: software topics

Overview: What to hide
Basic: VLIW Design Principle
Designing a VLIW ISA for Embedded Systems
Instruction-set Encoding

Terminology: Fundamental RISC-like minimal unit of work
Instruction:
-Fundamental unit of encoding
-Refers to a parallel set of operations
Bundle: a memory-aligned encoding unit
-VEX calls syllable (the min-sized encoding unit)

The ISA allows the designer to treat the processor as a black box.
Understanding the ISA can help determine processor to use for a given system.

Delay slots of early RISC machines
Illusion of instant registers update in superscalar

VLIW Architecture
-Exposes a scheduler in the compiler
-Conversely, superscalar architecture hides this

Memory: off-chip, and not specialized
Registers: fast, on-chip, connected to logics
Baseline model: sequential execution
Pipelining: Parallelism in time
-whether implementation is hidden or exposed is a design choice
-hidden: out-of-order

modern high performance processors:
15 to 20 stages: pentium 4 had a 20 stage pipeline

sequential program semantic
-tries to issue an instruction every clock cycle
-but, there are dependencies, control hazards and long latency instructions
-delays result in execution of < 1 instruction per cycle on an average VEX example: clock cycle and instruction Modern CPU Techniques: Pipelinig Execution stages are divided into several steps A later operation can share the resource used by the first operation in previous cycles Shared hardware can be pipeline e.g. Integer multiplier is pipelined. Instructions can be overlapped In embedded system, the choice of ISA is crucial! data or memory access: set a register to a fixed constant value control flow: branch, call functions arithmetic or logic: add, multiply, subtract, divide