modern high performance processors:
15 to 20 stages: pentium 4 had a 20 stage pipeline
sequential program semantic
-tries to issue an instruction every clock cycle
-but, there are dependencies, control hazards and long latency instructions
-delays result in execution of < 1 instruction per cycle on an average
VEX example: clock cycle and instruction
Modern CPU Techniques: Pipelinig
Execution stages are divided into several steps
A later operation can share the resource used by the first operation in previous cycles
Shared hardware can be pipeline
e.g. Integer multiplier is pipelined.
Instructions can be overlapped
In embedded system, the choice of ISA is crucial!
data or memory access: set a register to a fixed constant value
control flow: branch, call functions
arithmetic or logic: add, multiply, subtract, divide
