Overview: What to hide
Basic: VLIW Design Principle
Designing a VLIW ISA for Embedded Systems
Instruction-set Encoding
Terminology: Fundamental RISC-like minimal unit of work
Instruction:
-Fundamental unit of encoding
-Refers to a parallel set of operations
Bundle: a memory-aligned encoding unit
-VEX calls syllable (the min-sized encoding unit)
The ISA allows the designer to treat the processor as a black box.
Understanding the ISA can help determine processor to use for a given system.
Delay slots of early RISC machines
Illusion of instant registers update in superscalar
VLIW Architecture
-Exposes a scheduler in the compiler
-Conversely, superscalar architecture hides this
Memory: off-chip, and not specialized
Registers: fast, on-chip, connected to logics
Baseline model: sequential execution
Pipelining: Parallelism in time
-whether implementation is hidden or exposed is a design choice
-hidden: out-of-order
